Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to a method and apparatus for anisotropic etching and patterning of pure Cu and Cu-containing layers used in integrated circuits.
Description of the Related Art
Copper (Cu) is emerging as the metal of choice in a wide variety of semiconductor applications. Lower electrical resistivity, coupled with improved electromigration performance and increased stress migration resistance are important material properties that favor the use of Cu over aluminum (Al) in interconnect lines and contacts. The lower electrical resistance is critical since it allows signals to move faster by reducing the RC time delay. The superior resistance to electromigration, a common reliability problem in Al lines, means that Cu can handle higher power densities. An equally important benefit of using Cu over Al is that the manufacturing cost for a Cu metallization scheme can be lower due to new processing methods that reduce the number of manufacturing steps and alleviate the need for some of the most difficult steps.
The capability to process substrates anisotropically permits the production of integrated circuit features at precisely defined locations with sidewalls that are essentially perpendicular to the surface of a masked overlayer. The introduction of Cu into multilevel metallization architecture requires new processing methods for Cu patterning. Because Cu is difficult to dry etch, new process schemes have been developed for Cu patterning.
The damascene approach is based on etching features in the dielectric material, filling them with Cu metal, and planarizing the top surface by chemical mechanical polishing (CMP). Dual damascene schemes integrate both the contacts and the interconnect lines into a single processing scheme. However, Cu CMP technology is challenging and it has difficulty defining extremely fine features. In addition, CMP suffers from yield-detracting problems of scratching, peeling, dishing and erosion.
An alternative to the damascene approach is patterned etching of a Cu layer. The patterned etch process involves deposition of a Cu layer on a substrate, the use of a patterned hard mask or photoresist over the Cu-containing layer, patterned etching of the Cu layer using a reactive ion etching (RIE) process; and deposition of dielectric material over the patterned Cu-containing layer. Patterned etching of Cu can have advantages over damascene processes since it is easier to etch fine Cu patterns and then deposit a dielectric layer onto the Cu pattern, than it is to get barrier layer materials and Cu metal to adequately fill small feature openings in a dielectric film.
Patterned etching using RIE processes is characterized by relatively low pressures and high ion bombardment energies. While ion bombardment is needed to achieve the desired degree of etch anisotropy, it is also responsible for secondary damage to the underlying microstructure. As semiconductor devices have become increasingly more integrated and new advanced materials, such as copper and low-k dielectric materials, have been introduced to improve the circuit properties, the damage caused by fabrication processes presents an increasingly serious problem. A leading reason for damage formation is essentially the incidence of energetic particles, such as ions and UV photons, from the plasma environment to the substrate surface.
The primary etch reagent for removing Cu layers is traditionally a chorine-containing gas in gas mixture that includes argon (Ar). Removal of pure Cu layers and Cu-containing layers with high Cu-content using chlorine plasma essentially involves physical sputtering of the low-volatility CuClx surface layer by energetic ions in the plasma. The Cu removal rates are very low when using this method and another drawback is that the sputtered CuCx coats the chamber walls and this requires periodic cleaning of the etching chamber. An equally serious problem is encountered when high-aspect-ratio features are etched in chlorine plasma and the sputtered CuClx products redeposit on the feature sidewalls where the effects of physical sputtering are reduced.
When the abovementioned chlorine-based etching process is carried out at elevated temperatures (>200° C.) to increase the volatility of the reacted Cu-containing layer, corrosion can occur due to the accumulated CuClx etch residues on the surface. If these residues are not removed by a post-etch cleaning step, they can cause continuing corrosion of the Cu even after the application of a protective layer over the etched features.
Other energy sources have been suggested to increase the etching rate. These approaches include exposing the etching surface to UV or IR light sources to accelerate desorption of CuClx from the etching surface. However, these approaches are not practical for semiconductor batch processing of large substrates due to poor etch uniformity, high cost and added equipment complexity, and reliability problems.
Accordingly, it is desirable to develop a method for anisotropic etching in semiconductor manufacturing using plasmas that are essentially free of energetic ions and photon particles. Such particles are ordinarily required to achieve anisotropic etch with atomic oxygen plasmas in the prior art, but cause secondary damage to the underlying substrate. Furthermore, the reaction products should be highly volatile and easily removed from the etched substrate. In addition, the aforementioned limitations that are encountered when etching Cu-containing layers using conventional chlorine chemistry, show that there is a need for new low temperature dry etching methods in semiconductor manufacturing using chemical approaches that do not involve chlorine-based reactants.